Please refer to FIG. 1 which is a schematic block diagram illustrating a typical internal structure of a personal computer in communication with an external network. The personal computer includes a microprocessor 10, a north bridge chip 11, a south bridge chip 12, a memory 111 and a network interface card 121. The memory 111 is connected to the north bridge chip 11. The network interface card 121 is connected to the north bridge chip 11 via a peripheral component interconnect (PCI) bus. The network interface card 121 includes a media access controller (MAC) 1211 and a physical layer device (PHY) 1212. In some configurations, the MAC 1211 could be directly integrated into the south bridge chip 12. The PHY 1212 is used for connecting to an external network.
When transceiving data packets, the MAC 1211 issues interrupt signals to the microprocessor 10 for interrupting hardware. The microprocessor 10 suspends the proceeding job to perform an interrupt service routine (ISR) for the driver of the MAC 1211. FIG. 2A is a schematic waveform diagram illustrating concerned signals of the MAC 1211 and its driver when receiving data packets. When the data receiving signal RxDV is at a high level, it represents that the MAC is receiving data packets. When the data receiving signal RxDV switches from the high level to a low level, it represents that one data packet is completely received. Meanwhile, the interrupt signal INTA is outputted as a low-level pulse signal and the register value of the perfect Rx interrupt mask (PRXM) is switched from logic “1” into logic “0”. The microprocessor 10 proceeds the ISR and the defer procedure code (DPC) operations in response to the interrupt signal INTA to allow the operating system (OS) to process the data packet, which is received by the MAC 1211 and stored in the memory 111, and release the occupied memory space. After finishing the DPC operation, a section of program codes EnableINT is executed to recover the mask for the register value of the PRXM from logic “0” back to logic “1”. Thus, another interrupt signal can be generated upon completing receiving the data packet.
FIG. 2B is a schematic waveform diagram illustrating concerned signals of the MAC 1211 and its driver when transmitting out data packets. When the data transmitting signal TxDV is at a high level, it represents that the MAC is transmitting out data packets. When the data transmitting signal TxDV switches from the high level to a low level, it represents that the transmission of one data packet is finished. Meanwhile, the interrupt signal INTA is outputted as a low-level pulse signal, and the register value of the perfect Tx interrupt mask (PTXM) is switched from logic “1” into logic “0”. The microprocessor 10 proceeds the ISR and the defer procedure code (DPC) operations to allow the operating system (OS) to free the memory space occupied by the transmitted data packet. After finishing the DPC operation, likewise, a section of program codes EnableINT is executed to recover the mask for the register value of the PTXM form logic “0” back to logic “1”. Thus, another interrupt signal can be generated when finishing a new the data packet transmission.
As shown in FIGS. 2A and 2B, the MAC 1211 asserts the interrupt signal, i.e. INTA of the low-level pulse signal, whenever one data packet is received or transmitted. It results in that the operation resource of the microprocessor 10 is frequently occupied. In addition, particularly for the wideband network, the data flow between the system and the MAC is huge. Hence, the microprocessor is frequently interrupted, so the operation resource of the microprocessor 10 will be frequently occupied to deteriorate the performance of the system. Moreover, in some operating systems, a hang-up situation is likely to occur due to frequent hardware interruption.
Therefore, the purpose of the present invention is to timely generate an interrupt signal so as to deal with the above situations encountered in the prior art.